V7-A Cortex CPUs training courses
Cortex-A5, A7, A8, A9, A15 and A17 training courses (Armv7-A): MMU, caches and coherency, exceptions, GIC, TrustZone and debug, for SoC designers and low-level software developers.
Training catalogue
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Courses
ARM_CA_A17
V7-A Cortex CPUs
Cortex®-A17
This course explains the hardware and software architecture of the Cortex-A17 to enable participants to efficiently design an SoC based on this CPU, verify it, and develop low level software, implementing the features offered by the CPU: MMU, cache, exceptions, security, virtualization and multicore
ARM_CA_A15
V7-A Cortex CPUs
Cortex®-A15
This course explains the hardware and software architecture of the Cortex-A15 to enable participants to efficiently design an SoC based on this CPU, verify it, and develop low level software, implementing the features offered by the CPU: MMU, cache, exceptions, security, virtualization and multicore
ARM_CA_A9
V7-A Cortex CPUs
Cortex®-A9
This course explains the hardware and software architecture of the Cortex-A9 to enable participants to efficiently design an SoC based on this CPU, verify it, and develop low level software, implementing the features offered by the CPU: MMU, cache, exceptions, security, multicore
ARM_CA_A8
V7-A Cortex CPUs
Cortex®-A8
This course explains the hardware and software architecture of the Cortex-A8 to enable participants to efficiently design an SoC based on this CPU, verify it, and develop low level software, implementing the features offered by the CPU: MMU, cache, exceptions, security, multicore
ARM_CA_A7
V7-A Cortex CPUs
Cortex®-A7
This course explains the hardware and software architecture of the Cortex-A7 to enable participants to efficiently design an SoC based on this CPU, verify it, and develop low level software, implementing the features offered by the CPU: MMU, cache, exceptions, security, virtualization and multicore
ARM_CA_A5
V7-A Cortex CPUs
Cortex®-A5
This course explains the hardware and software architecture of the Cortex-A5 to enable participants to efficiently design an SoC based on this CPU, verify it, and develop low level software, implementing the features offered by the CPU: MMU, cache, exceptions, security, multicore