Target audience
Architects, verification engineers, software developers
Hands-on
Based on GCC toolchain and TRACE32 debugger and simulator
Agenda
DAY1
- Arm basics
- Cortex-A17 architecture
- Hardware implementation
- Instruction pipeline
DAY2
- TrustZone
- Virtualization extensions
- Page attributes
DAY3
- Introduction to memory management unit
- MMU- short descriptors
- MMU- LPAE
- System MMU, MMU-400
DAY4
- L1 and L2 caches
- Hardware cache coherency
- Exclusive resource management
- big.LITTLE operation
DAY5
- GICv2 and low power modes
- Generic timer
- Performance monitor
- CoreSight debug
DAY6
- V7-A instruction set summary
- Floating-point unit
- Embedded software development
Related products
Cortex-A17 CPU Software Package
Contact us for additional information
Included with every course
On-site session, contents tailored to your needs
Training manuals in PDF format
Certificate of completion for every attendee
Trainers who follow the vendors' train-the-trainer programmes
Questions
Can the course be tailored to our project?
Yes. You choose the chapters, how deep each one goes and the boards used in the labs. We send you the programme to review before the session.
Do the attendees get a certificate?
Yes. Every attendee receives a certificate of completion of the course.
Where does the session take place?
Usually at your premises. The trainer brings the evaluation boards used in the labs.
How many attendees can join?
Small or large groups: tell us how many engineers will attend when you request the course.
What course material do the attendees receive?
The training manuals in PDF format.
Who are the trainers?
Engineers who follow the vendors' train-the-trainer programmes and work on these devices in their own projects.
How do we book a session?
Use "Request this course" with the number of attendees, the place and the device of your project. We reply with the programme and agree on the dates with you.