For dedicated sessions at your training facilities, content can be tailored to further meet your needs
(Contact us for public workshops)
Certificate of Completion
A Certificate of Completion will be delivered upon completion of the training course
This course aims to enable participants to design, verify or debug AXI-based IPs or interconnects.
Participants get a detailed understanding of the AXI3, AXI4, and AXI5 protocols.
Cache coherency protocol extensions ACE is studied.
The following ARM interconnects are studied: NIC-400 (non-coherent), CCI-400 (coherent without snoop filter) and CCN-512 (with snoop filter and L3 cache).
ARM CPU architecture background is provided first in order to explain all transaction attributes and clarify transaction ordering rules.
AXI3 AND AXI4
AXI5 NEW FEATURES
INTERFACE AND DATA PROTECTION
LPD-500 LOW POWER DISTRIBUTOR
NIC-301 AND NIC-400 INTERCONNECTS
INTRODUCTION TO CACHE AND TLB COHERENCY
ACE4, ACE4-LITE AND ACE5, ACE5-LITE, ACE5-LiteACP
CCI-400 AND CCN-512 CACHE COHERENT INTERCONNECTS
MOVE.B IS MORE THAN A TRAINING CENTER
Trainers are also experts able to assist customers throughout the design process.
They also provide consulting services, design support and assistance.
Therefore, our trainers contribute to the success of our customers’ industrial projects by leveraging all of the technologies they master and teach.