Reference : ARM_AMBA_AXI
Course families : Processors > Arm CPUs and related technologies (AMBA and CoreSight) > AMBA buses and interconnects
Target Audience : Architects, verification engineers
Duration : 3 days, 7 hours a day
INTRODUCTION TO AMBA SPECIFICATIONS
TRUSTZONE ARCHITECTURE
EXCLUSIVE RESOURCE MANAGEMENT, SOFTWARE ASPECTS
MPU / MMU PAGE ATTRIBUTES
CACHE MEMORY
CACHE COHERENCY
AXI3 AND AXI4
AXI5 NEW FEATURES
INTERFACE AND DATA PROTECTION
AXI4-STREAM
AXI4-LITE, AXI5-LITE
LPD-500 LOW POWER DISTRIBUTOR
NIC-301 AND NIC-400 INTERCONNECTS
INTRODUCTION TO CACHE AND TLB COHERENCY
ACE4, ACE4-LITE AND ACE5, ACE5-LITE, ACE5-LiteACP
CCI-400 AND CCN-512 CACHE COHERENT INTERCONNECTS
Lectures with supporting slides, demos and case studies
Ordering issues (CDAS) are explained through practical use cases
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
