AMBA buses and interconnects training courses
AMBA training courses: AXI4 and AXI5, AHB5 and APB4, and the AMBA 5 CHI coherent interconnect: transactions, ordering, coherency and verification, for SoC designers.
Training catalogue
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Courses
ARM_AMBA_AHB
AMBA buses and interconnects
AMBA AHB5 and APB4
This course aims to enable participants to design, verify or debug AHB-based IPs or interconnects. Participants get a detailed understanding of the AHB-5 and APB-4 protocols and CoreLink SIE-200 interconnect. ARM CPU architecture background is provided first in order to explain all transaction attributes and clarify transaction ordering rules.
ARM_AMBA_CHI
AMBA buses and interconnects
AMBA5 CHI
This course aims to enable participants to design, verify or debug CHI-based IPs or interconnects. Participants get a detailed understanding of the CHI protocols, up to issue H, and will study the operation of the Arm CMN-700 CHI interconnect. CPU architecture background is provided first in order to explain all transaction attributes and clarify transaction ordering rules.
ARM_AMBA_AXI
AMBA buses and interconnects
AMBA AXI4 and AXI5
This course aims to enable participants to design, verify or debug AXI-based IPs or interconnects. Participants get a detailed understanding of the AXI3, AXI4, and AXI5 protocols, up to issue L. New features, such as RME and credited transport are fully covered. Cache coherency protocol extensions ACE is studied through multiple scenarios, that illustrate the various types of snoop request. The following Arm interconnects are studied: NIC-450 (non-coherent), CCI-400 (coherent without snoop filter) and CCN-512 (with snoop filter and L3 cache). Arm CPU architecture background is provided first in order to explain all transaction attributes and clarify transaction ordering rules.