V9-A Cortex CPUs training courses
Armv9-A training courses: the architecture and the Cortex-A320 to Cortex-A725 and Cortex-X925 cores, SVE2, memory tagging, security and virtualization, DynamIQ Shared Unit.
Training catalogue
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Courses
ARM_V9A
Processors
Arm V9-A Architecture
This course explains the ARM V9-A, V9.1A, V9.2-A, and V9.3-A software architectures to enable participants to efficiently develop low level software, implementing the features offered by the CPU: MMU, cache, exceptions, security, virtualization and multicore. This course does not detail implementation dependent features implemented in particular ARM V9-A processor cores. Refer to the V9-A core related courses.
ARM_CA_X925
Arm CPUs and related technologies (SMMU, AMBA, CoreSight)
Cortex®-X925
This course explains the hardware and software architecture of the Cortex-X925 and DSU-120 to enable participants to efficiently design an SoC based on this CPU, verify it, and develop low level software, implementing the features offered by the CPU: MMU, cache, exceptions, security, virtualization and multicore.
ARM_CA_X4
Arm CPUs and related technologies (SMMU, AMBA, CoreSight)
Cortex®-X4
This course explains the hardware and software architecture of the Cortex-X4 and DSU-120 to enable participants to efficiently design an SoC based on this CPU, verify it, and develop low level software, implementing the features offered by the CPU: MMU, cache, exceptions, security, virtualization and multicore.
ARM_CA_X2
Arm CPUs and related technologies (SMMU, AMBA, CoreSight)
Cortex®-X2 & Cortex®-X3
This course explains the hardware and software architecture of the DSU-110, Cortex-X2 and Cortex-X3 to enable participants to efficiently design an SoC based on this CPU, verify it, and develop low level software, implementing the features offered by the CPU: MMU, cache, exceptions, security, virtualization and multicore. Differences between Cortex-X2 and Cortex-X3 are highlighted.
ARM_CA_A720
Arm CPUs and related technologies (SMMU, AMBA, CoreSight)
Cortex®-A720/A720AE & Cortex®-A725
This course explains the hardware and software architecture of the Cortex-A720 and Cortex-A720AE, as well as DSU-120 to enable participants to efficiently design an SoC based on this CPU, verify it, and develop low level software, implementing the features offered by the CPU: MMU, cache, exceptions, security, virtualization and multicore. New features offered by Cortex-A725 are highlighted.
ARM_CA_A710
Arm CPUs and related technologies (SMMU, AMBA, CoreSight)
Cortex®-A710 & Cortex®-A715
This course explains the hardware and software architecture of the Cortex-A710 and Cortex-A715 to enable participants to efficiently design an SoC based on this CPU, verify it, and develop low level software, implementing the features offered by the CPU: MMU, cache, exceptions, security, virtualization and multicore. Differences between Cortex-A710 and Cortex-A715 are highlighted.
ARM_CA_A520
Arm CPUs and related technologies (SMMU, AMBA, CoreSight)
Cortex®-A520 & Cortex®-A520AE
This course explains the hardware and software architecture of the Cortex-A520 and DSU-120 to enable participants to efficiently design an SoC based on this CPU, verify it, and develop low level software, implementing the features offered by the CPU: MMU, cache, exceptions, security, virtualization and multicore. Safety features of Cortex-A520AE are detailed, particularly the lockstep mode.
ARM_CA_A510
V9-A Cortex CPUs
Cortex®-A510
This course explains the hardware and software architecture of the Cortex-A510 to enable participants to efficiently design an SoC based on this CPU, verify it, and develop low level software, implementing the features offered by the CPU: MMU, cache, exceptions, security, virtualization and multicore.
ARM_CA_A320
Arm CPUs and related technologies (SMMU, AMBA, CoreSight)
Cortex®-A320
This course explains the hardware and software architecture of the Cortex-A320 and DSU-120T to enable participants to efficiently design an SoC based on this CPU, verify it, and develop low level software, implementing the features offered by the CPU: MMU, cache, exceptions, security, virtualization and multicore.