LPDDR memories training courses
LPDDR training courses: LPDDR2 to LPDDR5/5X and LPDDR6, low-power DRAM architecture, commands, initialisation and training, power states and controller design.
Training catalogue
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Courses
DRAM_LPDDR6
LPDDR memories
LPDDR6
This course aims to enable participants to design, verify or debug LPDDR6 memories and controller IPs. Attendees will get a detailed understanding of the LPDDR6 Jedec standard. They will learn the protocol used to exchange data with LPDDR6 devices and they will study the analog features, particularly the various calibrations procedures.
DRAM_LPDDR5
LPDDR memories
LPDDR5 / LPDDR5X
This course aims to enable participants to design, verify or debug LPDDR5 / LPDDR5X memories and controller IPs. Attendees will get a detailed understanding of the LPDDR5 Jedec standard. They will learn the protocol used to exchange data with LPDDR5/5X devices and they will study the analog features, particularly the various calibrations procedures.
DRAM_LPDDR4
LPDDR memories
LPDDR4
This course aims to enable participants to design, verify or debug LPDDR4 and LPDDR4X memories and LPDDR4/4X controller IPs. Attendees will get a detailed understanding of the LPDDR4 Jedec standard and LPDDR4X new features. They will learn the protocol used to access LPDDR4/4X devices and will study the operation of the NXP i.MX8 LPDDR4 controller as an example of implementation.
DRAM_LPDDR3
LPDDR memories
LPDDR3
This course aims to enable participants to design, verify or debug LPDDR3 memories and LPDDR3 controller IPs. Attendees will get a detailed understanding of the LPDDR3 Jedec standard. They will learn the protocol used to access LPDDR3 devices and will study the operation of the NXP i.MX7 LPDDR3 controller as an example of implementation.
DRAM_LPDDR2
LPDDR memories
LPDDR2
This course aims to enable participants to design, verify or debug LPDDR2 memories and LPDDR2 controller IPs. Attendees will get a detailed understanding of the LPDDR2 Jedec standard. They will learn the protocol used to access LPDDR2 devices and will study the operation of the NXP i.MX6 LPDDR2 controller as an example of implementation.