Reference : DRAM_LPDDR4
Course families : DRAM memories > LPDDR memories
Target Audience : Architects, board designers, verification engineers, validation engineers
Duration : 2 days, 7 hours a day
INTRODUCTION TO DRAM
LPDDR4 NEW FEATURES
LPDDR4 PACKAGE PINOUT & ADDRESSING
FUNCTIONAL DESCRIPTION
LPDDR4 COMMAND DEFINITIONS AND TIMING DIAGRAMS
ON DIE TERMINATION (ODT) FOR COMMAND/ADDRESS BUS
TRAINING PROCEDURES
ELECTRICAL CHARACTERISTICS
LPDDR4X NEW FEATURES
iMX8 LPDDR4 CONTROLLER
Lectures with supporting slides, demos and case studies
Practical uses cases complement the theoretical explanations
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
LPDDR3 LPDDR5 / LPDDR5X