DDR memories training courses
DDR SDRAM training courses: DDR2, DDR3/DDR3L, DDR4 and DDR5: architecture, commands, initialisation and training, timings and memory controller design.
Training catalogue
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Courses
DRAM_DDR5
DDR memories
DDR5
This course aims to enable participants to design, verify or debug DDR5 memories and DDR5 controller IPs. Attendees will get a detailed understanding of the DDR5 Jedec standard. They will learn the protocol used to access DDR5 devices and the analog characteristics.
DRAM_DDR4
DDR memories
DDR4
This course aims to enable participants to design, verify or debug DDR4 memories and DDR4 controller IPs. Attendees will get a detailed understanding of the DDR4 Jedec standard. They will learn the protocol used to access DDR4 devices and will study the operation of the NXP T1040 DDR4 controller as an example of implementation.
DRAM_DDR3
DDR memories
DDR3 / DDR3L
This course aims to enable participants to design, verify or debug DDR3 memories and DDR3 controller IPs. Attendees will get a detailed understanding of the DDR3 Jedec standard. They will learn the protocol used to access DDR3 devices and will study the operation of the NXP i.MX6 DDR3 controller as an example of implementation.
DRAM_DDR2
DDR memories
DDR2
This course aims to enable participants to design, verify or debug DDR2 memories and DDR2 controller IPs. Attendees will get a detailed understanding of the DDR2 Jedec standard. They will learn the protocol used to access DDR2 devices and will study the operation of the NXP MPC5645S DDR2 controller as an example of implementation.