PCI-SIG member: PCI Express from Gen 1 to Gen 8

MOVE.B is a member of the PCI-SIG, the consortium of the industry that develops the PCI Express specifications. Membership gives our trainers the specifications, their drafts and the work of the PCI-SIG working groups as they progress: each of our PCI Express courses is updated with the revision it covers, and the next generation is prepared while its specification is still a draft.

Our courses explain PCI Express from the specification to the silicon, for the engineers who design controllers and PHYs, integrate PCIe in an SoC or on a board, write drivers and firmware, or validate links in the lab: physical layer, link training and equalization, data link and transaction layers, power management, virtualization, errors and compliance.

PCI Express generations and our courses

Also on PCI Express: Mobile PCI Express (M-PCIe), the PCIe protocol over the MIPI M-PHY, and CXL (Compute Express Link), the cache-coherent memory and accelerator protocol that runs over the PCIe physical layer. All of them are in our general purpose buses family.

Where the specifications stand

Last reviewed: October 2026.

• PCIe 8.0: draft 0.5 released to the members in May 2026, after draft 0.3 in September 2025. 256.0 GT/s per lane, 1 TB/s in both directions on an x16 link, a new connector technology under evaluation, latency and FEC targets under review. The final specification is planned for 2028.
• PCIe 7.0: released in June 2025, 128.0 GT/s, 512 GB/s in both directions on an x16 link. Test equipment and silicon are being shown; preliminary compliance testing is planned for 2027 and the first Integrators List for 2028.
• PCIe 6.4 and 7.0: an Engineering Change Notice for optical-aware retimers carries PCI Express over optical fibre between hosts, switches and devices.
• CopprLink: PCI-SIG’s internal and external cables for PCIe 5.0 and 6.0 (32.0 and 64.0 GT/s); the PCIe 7.0 version is in preparation.

Each new revision goes into our courses: a team that starts a Gen 6 or Gen 7 design today learns the generation it will build, and the differences with the one it knows.

PCI Express design support

Beyond training, our engineers help the teams that implement PCIe links: schematics and pre-layout reviews, board bring-up, link training and equalization issues, drivers. A course can be tailored to your controller, your PHY or your SoC, with your questions on the agenda.