Reference : CVT_GP_PCIE5
Course families : Connectivity > General purpose buses
Target Audience : Architects, board designers, verification engineers, characterization engineers, firmware developers
Duration : 6 days, 7 hours a day
INTRODUCTION TO PCI EXPRESS
SUMMARY OF PCIE GEN1 AND GEN2 PHYSICAL LAYER
THE PHYSICAL LAYER- LOGICAL SUB-BLOCK
THE PHYSICAL LAYER – GEN3, GEN4 AND GEN5 ANALOG SUB-BLOCK
CHARACTERIZING A PCI EXPRESS INTERFACE
ASIC DESIGN- PIPE INTERFACE
MECHANICAL FORMATS
POWER MANAGEMENT
LINK LAYER STATE MACHINE
PACKET ROUTING
TLP ACKNOWLEDGEMENT
FLOW CONTROL
TRANSACTION ORDERING
QUALITY OF SERVICE
PACKET FORMAT
INTERRUPT MANAGEMENT
ERROR MANAGEMENT
THE CONFIGURATION SPACE
SR-IOV AND FEATURES THAT FACILITATE I/O VIRTUALIZATION
PROCESS ADDRESS SPACE ID (PASID)
HOT PLUG
CACHE MANAGEMENT
PROTOCOL MULTIPLEXING
PRECISION TIME MEASUREMENT
ATOMIC TRANSACTIONS
Lectures with supporting slides, use of projector.
PCIe traffic capture with Teledyne Lecroy analyzer complements the theoretical explanations.
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
PCI EXPRESS GEN3 & GEN4 PCI EXPRESS GEN6