Non-intrusive trace
ETM generates trace packets in hardware, in parallel with core execution. No code instrumentation, no probe effect, no timing distortion.
ChipTrace®
Non-intrusive hardware trace acquisition for Arm®-based SoCs
ChipTrace uses the Arm® CoreSight™ on-chip debug infrastructure (ETM, ETF, CSTF, ETR, TPIU) to capture instruction-level execution traces at full CPU clock speed. The trace path is purely hardware: zero instrumentation, zero CPU overhead, cycle-accurate timestamps.
Ref: Arm IHI 0029E — CoreSight Architecture Specification v3.0
Arm, Cortex and CoreSight are trademarks or registered trademarks of Arm Limited (or its subsidiaries or affiliates) in the US and/or elsewhere. ChipTrace is an independent product and is not affiliated with or endorsed by Arm Limited.
Technical overview
Full-speed capture
Trace data is output on the ATB (AMBA Trace Bus) at core clock speed. No sampling, no dropped packets when ETF buffering is correctly sized.
CoreSight native
ChipTrace configures the on-chip CoreSight components directly via APB register access: ETM, STM, TMC (ETF, ETB, ETR), CSTF funnels, Replicator, Timestamp genererator. No proprietary hardware required.
TRACE32 compatible
ChipTrace integrates with Lauterbach TRACE32 via PRACTICE scripts for CoreSight path setup. Configuration follows the Lauterbach app note "Setup of the Debugger for a CoreSight System" (app_arm_coresight.pdf).
Application domains
Automotive (ISO 26262)
ASIL-D projects on S32G gateway SoCs require proof of deterministic execution paths. Hardware trace provides objective evidence of code coverage and worst-case execution time without altering the test conditions.
Aerospace (DO-178C)
Certification authorities accept hardware trace as structural coverage evidence (MC/DC, statement, branch). The non-intrusive nature of ETM trace means test results are not invalidated by probe effects.
RTOS timing analysis
Measure actual context switch latency, ISR entry-to-exit time, and lock hold duration from the trace stream. Results are cycle-accurate and obtained on the production binary, not an instrumented build.
Multicore correlation
On heterogeneous SoCs (e.g. S32G2: A53 + M7), ChipTrace correlates traces from all cores using the shared TSG timestamp. Inter-core communication sequences (shared memory, mailbox interrupts) appear on a single unified timeline.
Validated SoCs
NXP LS1043A
Network processor4x A53 (1.6 GHz)
Full CoreSight topology
LS1043A RM, debug ch.
Full CoreSight topology
LS1043A RM, debug ch.
Validated
NXP i.MX 8X
Applications processor2-4x A35 (1.2 GHz) + M4F
CoreSight ETM, funnel, TPIU
i.MX 8QXP RM, debug ch.
CoreSight ETM, funnel, TPIU
i.MX 8QXP RM, debug ch.
Validated
STM32H7 series
High-performance MCUM7 (480 MHz) + optional M4
ETM, ITM/DWT, SWO
RM0433, debug ch.
ETM, ITM/DWT, SWO
RM0433, debug ch.
Validated
AMD Zynq UltraScale+
SoC FPGA (ZCU102/106)4x A53 (1.5 GHz) + 2x R5F
ETM, ETF, funnel, TPIU, FTM
Zynq US+ TRM UG1085
ETM, ETF, funnel, TPIU, FTM
Zynq US+ TRM UG1085
Validated
NXP S32G2 / S32G3
Vehicle network processor4-8x A53 (1.3 GHz) + 3-4x M7
ETM, funnel, ETF, ITM, DWT, TPIU
S32G3 RM, debug ch.
ETM, funnel, ETF, ITM, DWT, TPIU
S32G3 RM, debug ch.
Validated
NanoXplore NG-Ultra
Rad-hard SoC FPGA4x R52 (600 MHz) + eFPGA
ETM-R52, funnel, TPIU
NG-ULTRA UM, debug ch.
ETM-R52, funnel, TPIU
NG-ULTRA UM, debug ch.
Validated
