This course explains the hardware and software architecture of the Cortex-X4 and DSU-120 to enable participants to efficiently design an SoC based on this CPU, verify it, and develop low level software, implementing the features offered by the CPU: MMU, cache, exceptions, security, virtualization and multicore.
Architects, verification engineers, software developers
Familiarity with high-end processor architecture.
See courses ARM_AMBA_AXI, ARM_AMBA_CHI, ARM_NEON and ARM_DEBUG_CRS600 (CoreSight).
Knowledge of PCIe Address Translation Service (ATS) is also recommended, see course CVT_GP_PCIE67.
Lectures with supporting slides, demos and case studies
Review and execution of practical examples, provided by MOVE.B, using GCC compiler and Lauterbach TRACE32 simulator.
Yes. You choose the chapters, how deep each one goes and the boards used in the labs. We send you the programme to review before the session.
Yes. Every attendee receives a certificate of completion of the course.
Usually at your premises. The trainer brings the evaluation boards used in the labs.
Small or large groups: tell us how many engineers will attend when you request the course.
The training manuals in PDF format.
Engineers who follow the vendors' train-the-trainer programmes and work on these devices in their own projects.
Use "Request this course" with the number of attendees, the place and the device of your project. We reply with the programme and agree on the dates with you.