For dedicated sessions at your training facilities, content can be tailored to further meet your needs
(Contact us for public workshops)
Certificate of Completion
A Certificate of Completion will be delivered upon completion of the training course
This course aims to enable participants to design, verify or debug CHI-based IPs or interconnects.
Participants get a detailed understanding of the CHI protocols, including issue E, and will study the operation of the CCN-512 CHI interconnect.
ARM CPU architecture background is provided first in order to explain all transaction attributes and clarify transaction ordering rules.
Prerequisites and related courses
Basic knowledge of a CPU or DSP
INTRODUCTION TO AMBA SPECIFICATIONS
EXCLUSIVE RESOURCE MANAGEMENT, SOFTWARE ASPECTS
MPU / MMU PAGE ATTRIBUTES
INTRODUCTION TO CHI
CHI ISSUE E NEW CACHE TRANSACTIONS
CACHE AND TLB COHERENCY
QUALITY OF SERVICE
CCN-512 CACHE COHERENT INTERCONNECT
MOVE.B IS MORE THAN A TRAINING CENTER
Trainers are also experts able to assist customers throughout the design process.
They also provide consulting services, design support and assistance.
Therefore, our trainers contribute to the success of our customers’ industrial projects by leveraging all of the technologies they master and teach.