This course aims to enable participants to design, verify or debug AHB-based IPs or interconnects. Participants get a detailed understanding of the AHB-5 and APB-4 protocols and CoreLink SIE-200 interconnect. ARM CPU architecture background is provided first in order to explain all transaction attributes and clarify transaction ordering rules.
Architects, verification engineers, MCU support engineers
Basic knowledge of a CPU or DSP
Lectures with supporting slides, demos and case studies
Ordering issues are explained through practical use cases
Yes. You choose the chapters, how deep each one goes and the boards used in the labs. We send you the programme to review before the session.
Yes. Every attendee receives a certificate of completion of the course.
Usually at your premises. The trainer brings the evaluation boards used in the labs.
Small or large groups: tell us how many engineers will attend when you request the course.
The training manuals in PDF format.
Engineers who follow the vendors' train-the-trainer programmes and work on these devices in their own projects.
Use "Request this course" with the number of attendees, the place and the device of your project. We reply with the programme and agree on the dates with you.