CoreSight SoC-600 training course
This course aims to describe all debug features offered by ARM CPUs in order to accelerate the debug time. Both CoreSight architecture and IPs will be studied.
This course aims to describe all debug features offered by ARM CPUs in order to accelerate the debug time. Both CoreSight architecture and IPs will be studied.
Architects, verification engineers, software developers and MCU support engineers
Familiarity with ARM Cortex CPUs
LS1043A NXP board, Lauterbach TRACE32 invasive and non-invasive debug tools
Lectures with supporting slides, demos and case studies
Debug features will be studied through practical debug scenario based on an LS1043A NXP board
Yes. You choose the chapters, how deep each one goes and the boards used in the labs. We send you the programme to review before the session.
Yes. Every attendee receives a certificate of completion of the course.
Usually at your premises. The trainer brings the evaluation boards used in the labs.
Small or large groups: tell us how many engineers will attend when you request the course.
The training manuals in PDF format.
Engineers who follow the vendors' train-the-trainer programmes and work on these devices in their own projects.
Use "Request this course" with the number of attendees, the place and the device of your project. We reply with the programme and agree on the dates with you.