Reference : ARM_CA_A5
Course families : Processors > Arm CPUs and related technologies (SMMU, AMBA, CoreSight) > V7-A Cortex CPUs
Target Audience : Architects, verification engineers, software developers
Duration : 5 days, 7 hours a day
ARM BASICS
CORTEX-A5 ARCHITECTURE
HARDWARE IMPLEMENTATION
INSTRUCTION PIPELINE
TRUSTZONE
PAGE ATTRIBUTES
MEMORY MANAGEMENT UNIT
L1 CACHES
HARDWARE CACHE COHERENCY
PL310 L2 CACHE
EXCLUSIVE RESOURCE MANAGEMENT
GIC, TIMERS AND LOW POWER MODES
PERFORMANCE MONITOR
CORESIGHT DEBUG
V7-A INSTRUCTION SET SUMMARY
FLOATING-POINT UNIT
EMBEDDED SOFTWARE DEVELOPMENT
Lectures with supporting slides, demos and case studies
Review and execution of practical examples, provided by MOVE.B, using GCC compiler and Lauterbach Trace32 debugger
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
