1
What you receive
Everything to trace, read back and decode, delivered as source.
The ChipTrace library
Your SoC's configuration and a driver for every CoreSight block, in plain C.
Reference applications
One per scenario, ready to run on your board, startup code included.
TRACE32 scripts and T32Pilot
Read the trace back, decode it, and validate every scenario automatically.
ChipTraceAnalyzer
Decodes the captures with your ELF, without a TRACE32 licence: execution, profile, coverage, a multi-core timeline. Desktop application and reports.
2
Integration in three steps
One library between your code and the CoreSight registers, a few lines in your code.
your code
Your application
bare-metal or RTOS, boot to fault handler
ChipTraceLib
ChipTrace library
your SoC's configuration and the drivers, in C
silicon
CoreSight hardware
already on your chip
✓ no OS, no dynamic allocation, no interrupt✓ runs only when you call it✓ delivered for your SoC✓ plain C, GNU Arm, AArch32 and AArch64
1
Build
Link the library delivered for your SoC.
2
Init at boot
Choose a predefined topology. Every block is stopped, the buffers armed, then the sources are configured and started: no trace lost at start. From then on, only the hardware works.
3
Close and save
On a fault, a watchdog warning or the end of a test: the buffer is kept in non-volatile memory, read over Ethernet or JTAG, decoded in TRACE32 or ChipTraceAnalyzer.
main.c · simplified
#include "ChipTrace.h"
int main(void)
{
2 ChipTrace_Init(CT_TOPOLOGY_ETF_CIRCULAR); /* only hardware from here */
run_application();
3 ChipTrace_Close(); /* keep the history */
}
3
Footprint and checklist
A few kilobytes of code, plus the trace buffer you choose.
| Measured on the reference | S32G3 A53, AArch64 | NG-Ultra R52, AArch32 |
|---|---|---|
| Library code | 17.2 KB | 4.1 KB |
| Configuration | 2.0 KB | 216 B |
| Trace buffer, per path kept | 16 KB | 32 KB |
The S32G3 offers eleven 16 KB trace buffers: keep only those of the paths you use.
Debug power. On before ChipTrace_Init(), usually by the boot ROM or the first boot stage.
CoreSight mapped. As device memory in the MPU or MMU.
A copy in non-volatile memory. After ChipTrace_Close(), with the data cache cleaned first if it is on.
4
Supported SoCs
All supported and validated on the board, each with its datasheet (free MOVE.B account).
5
Validated on the board: T32Pilot
Every reference application, run on the board and checked on what its trace holds.
T32Pilot, MOVE.B's test automation for TRACE32, builds each scenario, runs it to its end point, reads the trace back and checks it, unattended, with an HTML report per campaign. It comes with ChipTrace: run the same campaigns on your board, and open any capture in ChipTraceAnalyzer in one click.
6
Your SoC is not listed?
MOVE.B ports ChipTrace from the SoC's reference manual and your board.
The SoC configuration
Addresses, trace buffers, trigger mapping, the init and close sequences.
The startup code
Per core: vectors, MPU or MMU, linker scripts.
Validated on your hardware
Every capture path, with T32Pilot, and the TRACE32 scripts for the new CPU.
7
ChipTrace in your development flow
One library, from your first board to units in the field.
Bring-up
The reference applications check every trace path on your first board.
Integration
The library in your firmware: a few calls.
Validation
Your test campaigns run on the board, automated with T32Pilot.
In the field
Each unit keeps its last moments before a fault, in non-volatile memory.
Your SoC, your board: we set it up with you.
A demo on your hardware, the library integrated in your firmware, your team trained on the trace.
MOVE.B training
Learn the trace ChipTrace relies on
The CoreSight units ChipTrace programs, the cores it traces and the SoCs it runs on, each one a MOVE.B course.