ChipTrace®
Triggers & counters

Trace only what matters

A trace buffer holds 16 KB on S32G3 and the bug you are after is rare. ChipTrace programs the logic built into the CoreSight trace blocks: the hardware decides what to record, when, and on which core.
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How it works

The conditions, their logic and the actions are evaluated by the trace hardware.

The failure shows up on the thousandth call or after a mode change: a condition, not a time window. ChipTrace programs the condition once, at boot; the hardware then evaluates it at every instruction, with no code added and no core stalled.

CONDITIONSETM LOGICACTIONSAddress comparatorssingle address, range, single-shotData comparatorsdata address, data value (Cortex-M7)Context ID · VMIDwhich task, which virtual machinePMU eventsthrough the ETM external inputsDWT comparatorsCortex-M watchpointsCTI trigger inanother core, an interconnect probeResource selectorspick one or two conditions, invert, combineCounters16-bit, reload, chainingSequencerfour states, resetfed back as conditionsTrace on / offthe instruction trace windowData trace onloads and stores (Cortex-M7)Event packeta marker in the trace streamTrigger outto the CTI: other cores, sinks
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Seven building blocks

Each one programmed by the ChipTrace library.
ETM logic

Event packets

A marker in the trace at a chosen address, task or input.
Every run of the brake handler, without a printf.
ETM logic

Counters

Count any event; at zero, open the trace or write a marker.
Trace call 1000, not the 999 that worked.
ETM logic

Sequencer

Four states: trace only after A, then B.
The fault handler, but only after the switch to run mode.
What is recorded

Data trace

The address and value of loads and stores, on the ranges you choose (Cortex-M7).
Who overwrites the calibration table, and with which value.
What is recorded

DWT

Cortex-M7 watchpoints, PC sampling and interrupt trace.
Every write to a flag, with its value and the code behind it.
Beyond the ETM

Performance Monitor

Cortex-A53 counters: cycles, cache refills, exceptions, also as markers in the trace.
Count the task switches in one function, and see where each one happened.
Beyond the ETM

CTI

An event on one core starts the trace of another.
The Cortex-M7 writes a mailbox: the Cortex-A53 trace starts there.
Validated

74 board tests

On S32G3: Cortex-A53 42, Cortex-M7 32. Run and checked by T32Pilot.
How T32Pilot tests →
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Example: a frame sent the wrong way

The trace hardware starts the capture itself, with no code added to the application.
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The bug

In a gateway, one core receives the frames (Cortex-M7), another one routes them (Cortex-A53). Once in thousands of frames, one is sent the wrong way.
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What you ask

Record the routing core only after the receiving core has handed it a frame.
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What you get

The trace of that routing, and nothing else, kept to be read after the fault.
Next

Integration

Adding ChipTrace to your firmware: the library, the steps, the footprint.
MOVE.B training

Learn the logic behind the triggers

ETM resources, CTI, DWT and the Performance Monitor are covered in depth in MOVE.B's CoreSight and core courses.

Arm is a registered trademark, and CoreSight a trademark, of Arm Limited. TRACE32 is a registered trademark of Lauterbach GmbH. Other names are trademarks of their respective owners.