NXP Power QorIQ P-Series training courses
NXP QorIQ P-Series training courses (P1 to P5): e500v2, e500mc and e5500 multicore processors, DPAA networking, CoreNet, DDR, SerDes and boot.
NXP QorIQ P-Series training courses (P1 to P5): e500v2, e500mc and e5500 multicore processors, DPAA networking, CoreNet, DDR, SerDes and boot.

This course explains the architecture of the P5040 to enable participants to efficiently design a board and implement the integrated memory controllers and peripherals
This course explains the architecture of the P5020 to enable participants to efficiently design a board and implement the integrated memory controllers and peripherals
This course explains the architecture of the P4080 to enable participants to efficiently design a board and implement the integrated memory controllers and peripherals
This course explains the architecture of the P3041 to enable participants to efficiently design a board and implement the integrated memory controllers and peripherals
This course explains the architecture of the P2041 to enable participants to efficiently design a board and implement the integrated memory controllers and peripherals
This course explains the architecture of the P2020 to enable participants to efficiently design a board and implement the integrated memory controllers and peripherals
This course explains the architecture of the P1022 to enable participants to efficiently design a board and implement the integrated memory controllers and peripherals
This course explains the architecture of the P1021 to enable participants to efficiently design a board and implement the integrated memory controllers and peripherals
This course explains the architecture of the P1010 to enable participants to efficiently design a board and implement the integrated memory controllers and peripherals