Reference : POWER_QIQ_P_P1022
Course families : NXP CPUs, MCUs and MPUs > NXP POWER CPUs and MPUs > NXP Power QorIQ P-Series
Target Audience : Board designers, boot and driver software developers
Duration : 5 days, 7 hours a day
OVERVIEW
INTERCONNECT
L2 CACHE
HARDWARE IMPLEMENTATION
TRUST ARCHITECTURE
MEMORY CONTROLLERS
PROGRAMMABLE INTERRUPT CONTROLLER
DMA CONTROLLER
LOW SPEED SERIAL INTERFACES
PCI EXPRESS BRIDGE
SATA HOST CONTROLLER
DISPLAY INTERFACE UNIT
ENHANCED SECURE DIGITAL HOST CONTROLLER
SECURITY ENGINE
ENHANCED THREE SPEED ETHERNET CONTROLLERS
SYNCHRONOUS SERIAL INTERFACE (SSI)
TDM INTERFACE
USB CONTROLLER
SOC PERFORMANCE MONITOR AND DEBUG FEATURES
Lectures with supporting slides, demos and case studies
Review and execution of practical examples, provided by MOVE.B, using GCC compiler and Lauterbach Trace32 debugger
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
P1021 P2020