Reference : CVT_MS_SATA
Course families : Connectivity > Mass Storage interfaces
Target Audience : Architects, board designers, verification engineers, firmware developers
Duration : 3 days, 7 hours a day
ORIGINS OF THE SATA INTERFACE
SATA ARCHITECTURE
PHYSICAL LAYER
OUT-OF BAND AND PHY POWER STATES
PHY INTERFACE FOR SATA 3 - PIPE
LINK LAYER
ATA REGISTERS
TRANSPORT LAYER
COMMANDS
ADVANCED HOST CONTROLLER INTERFACE - AHCI
PORT MULTIPLIER
Lectures with supporting slides, demos and case studies
SATA traffic capture with Teledyne Lecroy analyzer complements the theoretical explanations
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
NVME 2.0 UNIVERSAL FLASH STORAGE (UFS)