Reference : NXP_ARM_IMX8MP
Course families : NXP CPUs, MCUs and MPUs > NXP Arm MPUs > i.MX MPUs and MCUsNXP Arm MPUs > i.MX MPUs and MCUs > i.MX8
Target Audience : Board designers, boot and driver software developers
Duration : 6 days, 7 hours a day
ARCHITECTURE OF i.MX8MP
INTERCONNECT
SHARING RESOURCES BETWEEN CORTEX-A53 AND CORTEX-M7
POWER, CLOCKING AND RESET
BOOT PROCESS
MEMORY CONTROLLERS
PCIE GEN3 BRIDGE
TIMERS
SMART DMA (SDMA)
ENHANCED SECURED DIGITAL HOST CONTROLLER (uSDHC)
USB3.0 AND USB2 2.0 CONTROLLERS
COMMUNICATION MODULES
VIDEO INTERFACES
VIDEO AND GRAPHICS MODULES
AUDIO MODULES
NEURAL PROCESSING UNIT
SECURITY OVERVIEW
CENTRAL SECURITY UNIT (CSU)
SECURE NON VOLATILE STORAGE (SNVS)
CRYPTOGRAPHIC ACCELERATION AND ASSURANCE MODULE (CAAM)
THE OCOTP CONTROLLER
HIGH ASSURANCE BOOT
Lectures with supporting slides, demos and case studies
Review and execution of practical examples, provided by MOVE.B, using GCC compiler and Lauterbach Trace32 debugger
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
i.MX8M