USB 3.2
Reference : CVT_GP_USB3
Course families : Connectivity > General purpose buses
Target Audience : Architects, board designers, verification engineers, firmware developers
Duration : 4 days, 7 hours a day
Reference : CVT_GP_USB3
Course families : Connectivity > General purpose buses
Target Audience : Architects, board designers, verification engineers, firmware developers
Duration : 4 days, 7 hours a day
ARCHITECTURAL OVERVIEW
DATA FLOW MODEL
PHYSICAL LAYER, DIGITAL PART
PHYSICAL LAYER, ANALOG PART
DEBUGGING A USB 3 INTERFACE
USB ON-THE-GO
PIPE INTERFACE
SUPER-SPEED INTER-CHIP - SSIC
LINK LAYER
PROTOCOL LAYER
DEVICE FRAMEWORK
HUB OPERATION
EXTENSIBLE HOST CONTROLLER INTERFACE- xHCI
UAS CLASS
AUDIO / VIDEO CLASS
Lectures with supporting slides, demos and case studies
USB3 traffic capture with Teledyne Lecroy analyzer complements the theoretical explanations
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content