Reference : POWER_QIQ_T_T1040
Course families : NXP CPUs, MCUs and MPUs > NXP POWER CPUs and MPUs > NXP Power QorIQ T-Series
Target Audience : Board designers, boot and driver software developers
Duration : 8 days, 7 hours a day
OVERVIEW
INTERCONNECT
PERIPHERAL ACCESS MANAGEMENT UNIT (PAMU)
CORENET PLATFORM CACHE
HARDWARE IMPLEMENTATION
TRUST ARCHITECTURE
MEMORY CONTROLLERS
PROGRAMMABLE INTERRUPT CONTROLLER
DMA CONTROLLER
LOW SPEED SERIAL INTERFACES
PCI EXPRESS BRIDGE
DISPLAY INTERFACE UNIT
ENHANCED SECURE DIGITAL HOST CONTROLLER
SATA HOST CONTROLLER
USB CONTROLLER
SECURITY ENGINE
PERFORMANCE MONITOR AND DEBUG FEATURES
DPAA OVERVIEW
ETHERNET MACS
QUEUE MANAGER
BUFFER MANAGER
FRAME MANAGER
PATTERN MATCH ENGINE
ETHERNET SWITCH OVERVIEW
MAC LAYER
ETHERNET SWITCH INGRESS PROCESSING
ETHERNET SWITCH SHARED QUEUE SYSTEM
ETHERNET SWITCH EGRESS PROCESSING
ETHERNET SWITCH LAYER2 FRAME FORWARDING
QUICC ENGINE- SYSTEM INTERFACE
QUICC ENGINE- BUFFER MANAGEMENT
QUICC ENGINE- UNIFIED COMMUNICATION CONTROLLERS
QUICC ENGINE- UCC HDLC CONTROLLER
QUICC ENGINE- UCC TRANSPARENT CONTROLLER
MULTI-CHANNEL CONTROLLER ON UCC– UMCC
Lectures with supporting slides, demos and case studies
Review and execution of practical examples, provided by MOVE.B, using GCC compiler and Lauterbach Trace32 debugger
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
T1024 T2080