Reference : NXP_ARM_LS1043A
Course families : NXP Arm MPUs > LayerScape MPUs > LS1
Target Audience : Board designers, boot and driver software developers
Duration : 6 days, 7 hours a day
ARCHITECTURE OF LS1043A
INTERCONNECT
SYSTEM MMU, MMU500
POWER, CLOCKING AND RESET
TRUST ARCHITECTURE
RUN CONTROL AND POWER MANAGEMENT
PCIE BRIDGE
MEMORY CONTROLLERS
MASS STORAGE INTERFACES
LOW SPEED SERIAL INTERFACES
ENHANCED DIRECT MEMORY ACCESS (eDMA)
QUEUE DIRECT MEMORY ACCESS (qDMA)
USB CONTROLLERS
FLEXTIMER MODULE
DPAA OVERVIEW
ETHERNET MACS
QUEUE MANAGER
BUFFER MANAGER
FRAME MANAGER
SECURITY ENGINE
QUICC ENGINE- SYSTEM INTERFACE
QUICC ENGINE- BUFFER MANAGEMENT
QUICC ENGINE- UNIFIED COMMUNICATION CONTROLLERS
QUICC ENGINE- UCC HDLC CONTROLLER
QUICC ENGINE- UCC TRANSPARENT CONTROLLER
MULTI-CHANNEL CONTROLLER ON UCC- UMCC
Lectures with supporting slides, demos and case studies
Review and execution of practical examples, provided by MOVE.B, using GCC compiler and Lauterbach Trace32 debugger
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
LS1028A LS1046A