Reference : ARM_CA_A65
Course families : Processors > Arm CPUs and related technologies (SMMU, AMBA, CoreSight) > V8-A Cortex CPUs
Target Audience : Architects, verification engineers, software developers
Duration : 6 days, 7 hours a day
CORTEX-A65(AE) CLUSTER BASED ON DYNAMIQ SHARED UNIT
SMT IMPLEMENTATION
HARDWARE IMPLEMENTATION
CORTEX-A65AE/DSU-AE
RELIABILITY, AVAILABILITY, AND SERVICEABILITY (RAS) EXTENSION
INSTRUCTION PIPELINE
INTRODUCTION TO ARM ARCHITECTURE V8-A
AARCH64 EXCEPTION MANAGEMENT
TRUSTZONE
VIRTUALIZATION EXTENSIONS
PAGE ATTRIBUTES
INTRODUCTION TO MEMORY MANAGEMENT UNIT
MMU- AARCH64 LPAE
SYSTEM MMU, MMU-600
L1, L2 AND L3 CACHES
HARDWARE CACHE COHERENCY
EXCLUSIVE RESOURCE MANAGEMENT
BIG / LITTLE OPERATION
GICv3, GICv4 AND LOW POWER MODES
GENERIC TIMER
PERFORMANCE MONITOR
CORESIGHT DEBUG
A64 INSTRUCTION SET SUMMARY
CRYPTOGRAPHY ENGINE
FLOATING-POINT UNIT
EMBEDDED SOFTWARE DEVELOPMENT
Lectures with supporting slides, demos and case studies
Review and execution of practical examples, provided by MOVE.B, using GCC compiler and Lauterbach Trace32 debugger
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
CORTEX®-A57 CORTEX®-A72