Reference : NXP_ARM_IMX93
Course families : NXP Arm MPUs > i.MX MPUs and MCUs > i.MX9
Target Audience : Board designers, boot and driver software developers
Duration : 5 days, 7 hours a day
ARCHITECTURE OF I.MX93
ARM CORES INTEGRATION
Cortex®-A55
Cortex®-M33
ETHOS®-U65 NPU
SHARING RESOURCES BETWEEN CORTEX®-A55 AND CORTEX®-M33
POWER, CLOCKING AND RESET
BOOT PROCESS
MEMORY CONTROLLERS
ANALOG MODULES
TIMERS
ENHANCED DMA (eDMA)
ENHANCED SECURED DIGITAL HOST CONTROLLER (uSDHC)
USB2 2.0 CONTROLLERS
AUDIO MODULES
COMMUNICATION MODULES
SECURITY OVERVIEW
EDGELOCK SECURE ENCLAVE (ELE)
VIDEO AND GRAPHICS MODULES
CRYPTOGRAPHIC ACCELERATION AND ASSURANCE MODULE (CAAM)
THE OCOTP CONTROLLER
Alternating lectures, trainer-driven hands-on practical examples, group interactions with the trainer, and self-reflection time.
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
