i.MX94
Reference : NXP_ARM_IMX94
Course families : NXP Arm MPUs > i.MX MPUs and MCUs > i.MX9
Target Audience : Board designers, Software developers
Duration : 6 days, 7 hours a day
Reference : NXP_ARM_IMX94
Course families : NXP Arm MPUs > i.MX MPUs and MCUs > i.MX9
Target Audience : Board designers, Software developers
Duration : 6 days, 7 hours a day
ARCHITECTURE OF i.MX94
SHARING RESOURCES BETWEEN CORTEX-A55 AND CORTEX-M33/M7
POWER, CLOCKING AND RESET
BOOT PROCESS
ENHANCED DMA (eDMA)
MEMORY CONTROLLERS
TIMERS
INTER-PERIPHERAL CROSSBAR SWITCH (XBAR)
FUNCTIONAL SAFETY
ANALOG MODULES
TSN SWITCH (NETC4.3)
ETHERCAT SUBORDINATE CONTROLLER (ESC)
LOW SPEED COMMUNICATION MODULES
AUDIO MODULES
USB2.0 AND USB2 3.0 CONTROLLERS
NEURAL PROCESSING UNIT
PCIE GEN3 BRIDGE
DISPLAY CONTROLLER
SECURITY OVERVIEW
TRUSTED RESOURCE DOMAIN CONTROLLER (TRDC)
EDGELOCK SECURE ENCLAVE (ELE)
OCOTP CONTROLLER
CRYPTOGRAPHIC ACCELERATION AND ASSURANCE MODULE (CAAM)
INLINE ENCRYPTION ENGINE (IEE) AND INLINE PRINCE ENCRYPTION AND DECRYPTION (IPED)
BATTERY BACKED SECURE MEMORY (BBSM)
Alternating lectures, trainer-driven hands-on practical examples, group interactions with the trainer, and self-reflection time.n
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content