Reference : NXP_ARM_IMX51
Course families : NXP Arm MPUs > i.MX MPUs and MCUs > i.MX5
Target Audience : Board designers, boot and driver software developers
Duration : 5 days, 7 hours a day
ARCHITECTURE OF i.MX51
INTERCONNECT
POWER, CLOCKING AND RESET
UBOOT
MEMORY CONTROLLERS
ENHANCED SECURE DIGITAL HOST CONTROLLER
USB CONTROLLERS
TIMERS
TRUSTZONE INTERRUPT CONTROLLER (TZIC)
SMART DMA (SDMA)
COMMUNICATION MODULES
VIDEO AND GRAPHICS MODULES
AUDIO MODULES
SECURITY OVERVIEW
CENTRAL SECURITY UNIT (CSU)
SYMMETRIC/ASYMMETRIC HASHING AND RANDOM ACCELERATOR (SAHARA)
HIGH ASSURANCE BOOT
Lectures with supporting slides, demos and case studies
Review and execution of practical examples, provided by MOVE.B, using GCC compiler and Lauterbach Trace32 debugger
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
