Reference : ARM_CM_M35P
Course families : Processors > Arm CPUs and related technologies (SMMU, AMBA, CoreSight) > V8-M Cortex CPUs
Target Audience : Architects, verification engineers, software developers
Duration : 4 days, 7 hours a day
CORTEX-M35P OVERVIEW
PIPELINE AND BUS MATRIX
HARDWARE IMPLEMENTATION
MEMORY SUBSYSTEM
INTRODUCTION TO V8-M ARCHITECTURE
MEMORY MODEL
SECURITY ATTRIBUTION UNIT (SAU) AND IMPLEMENTATION DEFINED ATTRIBUTION UNIT (IDAU)
MEMORY PROTECTION UNITS
SOFTWARE SECURITY FRAMEWORK
EXCEPTION MECHANISM WITHOUT SECURITY
EXCEPTION MECHANISM WITH SECURITY
ANTI-TAMPERING FEATURES
ARM V8-M MAINLINE PROGRAMMING
EXCLUSIVE RESOURCE MANAGEMENT
CMSIS
DEBUG
EMBEDDED SOFTWARE DESIGN
EFFICIENT CODING GUIDELINES
Alternating lectures, trainer-driven hands-on practical examples, group interactions with the trainer, and self-reflection time.
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
CORTEX®-M33 CORTEX®-M52