Reference : CVT_GP_SRIO
Course families : Connectivity > General purpose buses
Target Audience : Architects, board designers, verification engineers, firmware developers
Duration : 4 days, 7 hours a day
INTRODUCTION TO RAPIDIO
OVERVIEW OF THE PHYSICAL LAYER
THE PHYSICAL LAYER – 8b10b- LOGICAL SUB-BLOCK
THE PHYSICAL LAYER – 64b67b- NEW FEATURES LOGICAL SUB-BLOCK
THE PHYSICAL LAYER – ANALOG SUB-BLOCK
COMMON TRANSPORT LAYER
INPUT / OUTPUT- LOGICAL LAYER
MESSAGE PASSING- LOGICAL LAYER
GLOBAL SHARED MEMORY- LOGICAL LAYER
PACKET PRIORITY AND FLOW CONTROL
ERROR MANAGEMENT
SYSTEM BRINGUP
END-TO-END FLOW CONTROL
DATA STREAMING
VIRTUAL OUTPUT QUEUING EXTENSIONS
SESSION MANAGEMENT PROTOCOL
Lectures with supporting slides, demos and case studies
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
USB4 PCI EXPRESS GEN1 & GEN2