This course aims to enable participants to design, verify or characterize PCIE gen6 and gen7 IPs and links. Participants get a detailed understanding of the PCI Express protocol. The attendees will learn about PCI Express hardware and software implementation. Latest ECNs will be covered.
Architects, board designers, verification engineers, characterization engineers, firmware developers
This course only details the PCIe gen6/gen7 physical layer.
For full description of 2.5 and 5.0 GTps, refer to CVT_GP_PCIE12.
For full description of 8.0 and 16.0 and 32.0 GTps, refer to CVT_GP_PCIE5.
Lectures with supporting slides, use of projector.
Yes. You choose the chapters, how deep each one goes and the boards used in the labs. We send you the programme to review before the session.
Yes. Every attendee receives a certificate of completion of the course.
Usually at your premises. The trainer brings the evaluation boards used in the labs.
Small or large groups: tell us how many engineers will attend when you request the course.
The training manuals in PDF format.
Engineers who follow the vendors' train-the-trainer programmes and work on these devices in their own projects.
Use "Request this course" with the number of attendees, the place and the device of your project. We reply with the programme and agree on the dates with you.