This course aims to enable participants to design, verify or characterize PCIE gen3, gen4 and gen5 IPs and links. Participants get a detailed understanding of the PCI Express protocol. The attendees will learn about PCI Express hardware and software implementation. Latest ECNs will be covered.
Architects, board designers, verification engineers, characterization engineers, firmware developers
This course only provides a summary of PCIe gen1 & gen2 physical layer.
For full description of 2.5 and 5.0 GTps, Refer to CVT_GP_PCIE12.
An analyzer from Teledyne-Lecroy is used to capture and display PCI Express traffic to facilitate the understanding of the protocol.
Lectures with supporting slides, use of projector.
PCIe traffic capture with Teledyne Lecroy analyzer complements the theoretical explanations.
Yes. You choose the chapters, how deep each one goes and the boards used in the labs. We send you the programme to review before the session.
Yes. Every attendee receives a certificate of completion of the course.
Usually at your premises. The trainer brings the evaluation boards used in the labs.
Small or large groups: tell us how many engineers will attend when you request the course.
The training manuals in PDF format.
Engineers who follow the vendors' train-the-trainer programmes and work on these devices in their own projects.
Use "Request this course" with the number of attendees, the place and the device of your project. We reply with the programme and agree on the dates with you.