This course aims to enable participants to design, verify or debug NVME IPs and links. Participants get a detailed understanding of the NVME 2.4 protocol. Latest features, such as flexible data placement and Post-Quantum Cryptography, are covered. The attendees will learn about NVME hardware and software implementation.
Architects, board designers, verification engineers, firmware developers
Knowledge of PCIe is required, refer to CVT_GP_PCIE67.
Traffic capture from an analyzer developed by Lecroy facilitates the understanding of the protocol.
Lectures with supporting slides, demos and case studies
Analysis of NVME traces obtained with Teledyne Lecroy analyzer complements the theoretical explanations
Yes. You choose the chapters, how deep each one goes and the boards used in the labs. We send you the programme to review before the session.
Yes. Every attendee receives a certificate of completion of the course.
Usually at your premises. The trainer brings the evaluation boards used in the labs.
Small or large groups: tell us how many engineers will attend when you request the course.
The training manuals in PDF format.
Engineers who follow the vendors' train-the-trainer programmes and work on these devices in their own projects.
Use "Request this course" with the number of attendees, the place and the device of your project. We reply with the programme and agree on the dates with you.