Reference : MV_88F8040
Course families : Processors > Marvell Embedded Processors
Target Audience : Board designers, software developers
Duration : 5 days, 7 hours a day
ARCHITECTURE OF 88F8040
COHERENT INTERCONNECT
SYSTEM MMU, MMU500
POWER, CLOCKING AND RESET
INTEGRATED SERDES
INTERRUPT MANAGEMENT AND TIMERS
SECURE BOOT
POWER MANAGEMENT
MEMORY CONTROLLERS (DDR4 controller, NAND flash controller and Device Bus controller)
MASS STORAGE INTERFACES (SDIO 3.0 host controller and SATA controller)
PCIE BRIDGE
LOW SPEED SERIAL INTERFACES
SECURITY
DMA ENGINES
USB CONTROLLERS
FLEXTDM CONTROLLER
PACKET PROCESSOR OVERVIEW
MANAGEMENT WITH MULTIPLE CPUs
DESCRIPTOR MANAGEMENT QUEUING
HARDWARE BUFFER MANAGEMENT CONTROLLER
IN-LINE RECEIVE FUNCTIONS
TRANSMIT FUNCTIONS
PACKET MODIFICATION ENGINE
INTERRUPT CONTROLLER
MEMORY INTERFACE CONFIGURATION
PORT SUB-SYSTEM ADAPTER
TIME APPLICATION INTERFACE
TIMESTAMP
SECURITY ACCELERATOR
Lectures with supporting slides, use of projector.
Review and execution of practical examples, provided by MOVE.B, using GCC compiler and Lauterbach Trace32 debugger.
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
