Reference : AMD_VERSAL_P
Course families : Processors > AMD SoCs
Target Audience : Board designers, software developers
Duration : 3 days, 7 hours a day
ARCHITECTURE OF VERSAL PRIME SOCS
INTERCONNECT AND FIREWALLS
SYSTEM MMU, MMU500
POWER, CLOCKING AND RESET
PLATFORM BOOT
INTER-PROCESSOR INTERRUPTS
IO MUX
LPD DMA CONTROLLER
PMC DMA UNITS AND STREAM SWITCH
FUNCTIONAL SAFETY
MEMORY CONTROLLERS
PCIE BRIDGE
GIGABIT ETHERNET MAC
Lectures with supporting slides, use of projector.
Review and execution of practical examples, provided by MOVE.B, using GCC compiler and Lauterbach Trace32 debugger.
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
