This course aims to explain SVE2 SIMD instructions and C new operators to enable participants to vectorize, code and optimize DSP-like algorithms. Optimizations due to cache, MMU and branch accelerators will also be explained. Many labs, coded in C language, contribute to become familiar with this rich instruction set.
Software developers
Familiarity with ARM AArch64 architecture.
Based on GCC toolchain and Lauterbach simulator.
Lectures with supporting slides, demos and case studies.
Labs are based on GCC toolchain and TRACE32 simulator.
Yes. You choose the chapters, how deep each one goes and the boards used in the labs. We send you the programme to review before the session.
Yes. Every attendee receives a certificate of completion of the course.
Usually at your premises. The trainer brings the evaluation boards used in the labs.
Small or large groups: tell us how many engineers will attend when you request the course.
The training manuals in PDF format.
Engineers who follow the vendors' train-the-trainer programmes and work on these devices in their own projects.
Use "Request this course" with the number of attendees, the place and the device of your project. We reply with the programme and agree on the dates with you.