Reference : DRAM_HBM3
Course families : DRAM memories > HBM memoriesDRAM memories
Target Audience : Architects, board designers, verification engineers, validation engineers
Duration : 2 days, 7 hours a day
INTRODUCTION TO DRAM
HBM3 SPECIFIC FEATURES
HBM3 ORGANIZATION
CLOCKING
HBM3 PACKAGE DIE SPECIFICATION
INITIALIZATION
COMMAND DEFINITIONS
ROW COMMANDS
READ, WRITE, DATA BUS INVERSION AND ECC
MODE REGISTERS
POWER-MODE COMMANDS
INTERCONNECT REDUNDANCY REMAPPING
TEST METHODS
ELECTRICAL CHARACTERISTICS
Lectures with supporting slides, demos and case studies.
Practical uses cases complement the theoretical explanations.
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
HIGH BANDWIDTH MEMORY DRAM HBM1, HBM2