For dedicated sessions at your training facilities, content can be tailored to further meet your needs
(Contact us for public workshops)
Certificate of Completion
A Certificate of Completion will be delivered upon completion of the training course
This course aims to enable participants to design, verify or debug HBM memories and HBM controller IPs. Attendees will get a detailed understanding of the HBM Jedec standard. They will learn the protocol used to access HBM devices and will study the various test methods.
Prerequisites and related courses
Familiarity with Synchronous DRAM
INTRODUCTION TO DRAM
HBM SPECIFIC FEATURES
HBM PACKAGE DIE SPECIFICATION
DDR4 COMMAND DEFINITIONS
READ, WRITE, WRITE DATA MASK, DATA BUS INVERSION AND ECC
INTERCONNECT REDUNDANCY REMAPPING
MOVE.B IS MORE THAN A TRAINING CENTER
Trainers are also experts able to assist customers throughout the design process.
They also provide consulting services, design support and assistance.
Therefore, our trainers contribute to the success of our customers’ industrial projects by leveraging all of the technologies they master and teach.