This course aims to enable participants to design, verify or debug DDR2 memories and DDR2 controller IPs. Attendees will get a detailed understanding of the DDR2 Jedec standard. They will learn the protocol used to access DDR2 devices and will study the operation of the NXP MPC5645S DDR2 controller as an example of implementation.
Architects, board designers, verification engineers, validation engineers
Familiarity with Synchronous DRAM
Lectures with supporting slides, demos and case studies
Practical uses cases complement the theoretical explanations
MOVE.B offers consultancy services to review board schematics and pre-layout and to initialize memory controller registers from memory device’s data sheet.
MOVE.B can help you to fine tune the Priority Manager present in NXP MPC5465S DRAM Controller.
Contact MOVE.B for more information.
Yes. You choose the chapters, how deep each one goes and the boards used in the labs. We send you the programme to review before the session.
Yes. Every attendee receives a certificate of completion of the course.
Usually at your premises. The trainer brings the evaluation boards used in the labs.
Small or large groups: tell us how many engineers will attend when you request the course.
The training manuals in PDF format.
Engineers who follow the vendors' train-the-trainer programmes and work on these devices in their own projects.
Use "Request this course" with the number of attendees, the place and the device of your project. We reply with the programme and agree on the dates with you.