This course aims to enable participants to design, verify or debug AXI-based IPs or interconnects.
Participants get a detailed understanding of the AXI3, AXI4, and AXI5 protocols, up to issue L. New features, such as RME and credited transport are fully covered. Cache coherency protocol extensions ACE is studied through multiple scenarios, that illustrate the various types of snoop request.
The following Arm interconnects are studied: NIC-450 (non-coherent), CCI-400 (coherent without snoop filter) and CCN-512 (with snoop filter and L3 cache).
Arm CPU architecture background is provided first in order to explain all transaction attributes and clarify transaction ordering rules.