STM32 online trainings designed by MOVE.B

An overview of the architecture of the STM32H7RS: a Cortex-M7 with a small internal Flash, built to run its application from external memory.

A presentation of the STM32H7RS series: Cortex-M7 microcontrollers running up to 600 MHz, with a boot Flash and the application in external memory.

Two-dimensional addressing on the DMA channels of the STM32H7RS that support it: moving blocks of data with strides, for example a rectangle of an image.

Circular buffering and double buffering with the DMA of the STM32H7RS, built from linked-list items.

How the DMA of the STM32H7RS reports errors: the error types, their flags and the state of the channel after an error.

Control of the input and output of the linked-list items in the DMA of the STM32H7RS: how the channel loads the next item and signals its end.

Linked-list programming of the DMA of the STM32H7RS: a chain of transfer descriptors in memory that the channel runs without the CPU.

An overview of the DMA controllers of the STM32H7RS: their channels, ports and the features detailed in the other DMA modules.

The registers of a DMA channel of the STM32H7RS and how each transfer setting maps to them.

DMA transfers of the STM32H7RS seen from the hardware and from the software: bursts, data widths, packing and the HAL calls that set them up.

The general-purpose I/O ports of the STM32H7RS: pin modes, output drive and alternate functions.

The power controller of the STM32H7RS: supplies, voltage regulation and low-power modes. The core can be supplied by an LDO or an SMPS.

The 2D graphics processor of the STM32H7RS, which draws and transforms images for the display without the CPU.

The external memory manager and loader of the STM32Cube package for the STM32H7RS: how the boot code in internal Flash starts an application stored in external memory.

The RAM configuration of the STM32H7RS: ECC on the SRAMs and how SRAM is shared between the tightly coupled memories and the system.

The XSPI interfaces of the STM32H7RS, which connect serial Flash and RAM memories on up to sixteen data lines.

The security features of the STM32H7RS, described by what they add to or change from the STM32H5.

Asymmetric cryptography on the STM32H7RS with the public key accelerator: RSA and elliptic curve operations.

An introduction to the cryptographic peripherals of the STM32H7RS and the role of each one. Depending on the part, the STM32H7RS has AES, SAES, HASH, PKA and RNG units.

The STM32 cryptographic library on the STM32H7RS: the algorithms it provides and how it uses the hardware accelerators.

The hash processor and the random number generator of the STM32H7RS.

The memory cipher engine of the STM32H7RS, which encrypts and decrypts on the fly the code and data in external memory.

The root security services of the STM32H7RS: code in system memory that the device runs at reset, such as the secure installation of firmware.

Symmetric cryptography on the STM32H7RS: the AES and SAES units and their chaining modes.

An overview of the analog peripherals of the STM32H7RS.

The tools and software that support the STM32H7RS: STM32Cube configuration and programming tools, the firmware package and the boards.

A presentation of the STM32U0 series: ultra-low-power entry-level microcontrollers built on a Cortex-M0+, running up to 56 MHz.

The opening module of the STM32U0 online training: how the training is organised and where to start.

The Arm Cortex-M0+ processor as integrated in the STM32U0: a 32-bit core with a two-stage pipeline.

The debug support of the STM32U0: the Serial Wire Debug port, breakpoints and watchpoints, and how debug behaves in low-power modes.

The DMA controller of the STM32U0: memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers that leave the CPU free.

The DMA request multiplexer of the STM32U0, which connects any peripheral request to any DMA channel.

The extended interrupt and event controller of the STM32U0: GPIO and peripheral lines that raise interrupts or events, including wake-up from low-power modes.

The general-purpose I/O ports of the STM32U0: pin modes, output drive and alternate functions.

The interconnect matrix of the STM32U0: the direct connections between peripherals that work without the CPU or the DMA.

The nested vectored interrupt controller of the Cortex-M0+ in the STM32U0: interrupt priorities, preemption and the vector table.

The power controller of the STM32U0: supplies, voltage regulation and low-power modes. The module covers the low-power run mode and the Stop modes used by battery products.

The reset and clock controller of the STM32U0: the clock sources, the PLL and the clock tree of the system and peripherals. The low-speed oscillators that keep running in low-power modes are covered too.

The system configuration controller of the STM32U0: memory remapping and the settings of the system that do not belong to one peripheral.

The tamper detection and backup registers of the STM32U0: inputs that detect an intrusion and the registers kept when the main supply is off.

The embedded Flash memory of the STM32U0: organisation, read access, programming and erase. The Flash is read with 64-bit words and an ECC on each word.

The protections of the memories of the STM32U0: how code and data are protected against reading, writing or debug access.

The features of the STM32U0 that support functional safety, and the documents and libraries ST provides for a safety application.

The analog comparators of the STM32U0: input selection, output routing and use as a wake-up source.

The timers of the STM32U0: counting modes, input capture, output compare and PWM. The series has advanced-control, general-purpose and basic timers.

The low-power timer of the STM32U0, which keeps counting in Stop modes with a low-frequency clock or external pulses.

The real-time clock of the STM32U0: calendar, alarms and wake-up timer, kept running in low-power modes and on VBAT.

The tools and software that support the STM32U0: STM32Cube configuration and programming tools, the firmware package and the boards.

A presentation of the STM32H5 series: Cortex-M33 microcontrollers with TrustZone, running up to 250 MHz.

The bus matrix of the STM32H5: which masters reach which memories and peripherals.

The data cache of the STM32H5, which speeds up data accesses of the Cortex-M33 to external memories.

Two-dimensional addressing on the DMA channels of the STM32H5 that support it: moving blocks of data with strides, for example a rectangle of an image.

DMA transfers that continue while the STM32H5 is in a low-power mode, driven by peripheral requests without waking the CPU.

Circular buffering and double buffering with the DMA of the STM32H5, built from linked-list items.

How the DMA of the STM32H5 reports errors: the error types, their flags and the state of the channel after an error.

Control of the input and output of the linked-list items in the DMA of the STM32H5: how the channel loads the next item and signals its end.

Linked-list programming of the DMA of the STM32H5: a chain of transfer descriptors in memory that the channel runs without the CPU.

An overview of the general-purpose DMA of the STM32H5: its channels, ports and the features detailed in the other DMA modules.

The registers of a DMA channel of the STM32H5 and how each transfer setting maps to them.

DMA transfers of the STM32H5 seen from the hardware and from the software: bursts, data widths, packing and the HAL calls that set them up.

The extended interrupt and event controller of the STM32H5, with lines that can be set secure or privileged.

The GPIO ports of the STM32H5: modes, alternate functions and the security of each pin.

The instruction cache of the STM32H5, between the Cortex-M33 and the internal and external memories.

The power controller of the STM32H5: supplies, voltage regulation and low-power modes. Depending on the part, the core is supplied by an LDO or an SMPS.

The reset and clock controller of the STM32H5: the clock sources, the PLL and the clock tree of the system and peripherals. The series has three PLLs.

The embedded Flash memory of the STM32H5: organisation, read access, programming and erase. The Flash has two banks, ECC, and an area for keys stored in the option bytes.

The RAM configuration controller of the STM32H5: ECC on the SRAMs, write protection and erase.

An overview of the security architecture of the STM32H5: isolation, root of trust, protection of keys and of the debug port.

Asymmetric cryptography on the STM32H5 with the public key accelerator: RSA and elliptic curve operations.

An introduction to the cryptographic peripherals of the STM32H5 and the role of each one. Depending on the part, the STM32H5 has AES, SAES, HASH, PKA and RNG units.

The STM32 cryptographic library on the STM32H5: the algorithms it provides and how it uses the hardware accelerators.

How the STM32H5 opens its debug port once the product is closed: the owner proves its right with a password or a certificate.

The tamper detection of the STM32H5: passive and active tamper inputs and internal monitors, and the erase of secrets on detection.

How the STM32H5 stores and uses keys: hardware unique key, keys in the option bytes and keys loaded into SAES without software access.

The hash processor and the random number generator of the STM32H5.

The life cycle of a product built on the STM32H5, from an open device to a closed or locked one, and what each state allows.

The root security services of the STM32H5: code in system memory that the device runs at reset, such as the secure installation of firmware.

The Secure Manager of the STM32H5: secure services provided by ST in the secure world, used by the application through standard interfaces.

The security certifications obtained for the STM32H5 and what they mean for a product built on it.

Symmetric cryptography on the STM32H5: the AES and SAES units and their chaining modes.

Trusted Firmware-M on the STM32H5: building, provisioning and running the secure and non-secure images.

The analog-to-digital and digital-to-analog converters of the STM32H5.

An overview of the analog peripherals of the STM32H5 and of the modules that describe them.

The analog comparator of the STM32H5: input selection, output routing and use as a wake-up source.

The operational amplifiers of the STM32H5: standalone use, follower and programmable gain modes.

The voltage reference buffer of the STM32H5, which supplies the reference voltage of the ADC and DAC and can output it on a pin.

The I3C interface of the STM32H5, controller or target, for the MIPI I3C bus that follows I2C for sensors.

The low-power timer of the STM32H5, which keeps counting in Stop modes with a low-frequency clock or external pulses.

The STM32Cube firmware package of the STM32H5: drivers, middleware and examples.

A presentation of the STM32C0 series: entry-level microcontrollers built on a Cortex-M0+, running up to 48 MHz.

The interconnect matrix of the STM32C0: the direct connections between peripherals that work without the CPU or the DMA.

The power controller of the STM32C0: supplies, voltage regulation and low-power modes. The series runs from a single supply.

The backup registers of the STM32C0, which keep a few words of data through low-power modes.

The reset and clock controller of the STM32C0: the clock sources, the dividers and the clock tree of the system and peripherals. The internal 48 MHz oscillator runs the system at full speed without a PLL or an external crystal.

The system configuration controller of the STM32C0: memory remapping and the settings of the system that do not belong to one peripheral.

The embedded Flash memory of the STM32C0: organisation, read access, programming and erase. The Flash is read with 64-bit words and an ECC on each word.

The protections of the memories of the STM32C0: how code and data are protected against reading, writing or debug access.

The FDCAN controller of the STM32C092 parts: CAN 2.0 and CAN FD frames with a flexible data rate.

The USB full-speed device interface of the STM32C0 parts that have it, which can run without an external crystal thanks to the internal 48 MHz oscillator and the clock recovery system.

The timers of the STM32C0: counting modes, input capture, output compare and PWM. The series has an advanced-control timer and general-purpose timers.

The real-time clock of the STM32C0: calendar and alarm, kept running in the low-power modes.

The tools and software that support the STM32C0: STM32Cube configuration and programming tools, the firmware package and the boards.

A presentation of the STM32U5 series: an ultra-low-power family built on a Cortex-M33 with TrustZone, running up to 160 MHz.

The bus matrix of the STM32U5: which masters reach which memories and peripherals, and the paths that stay active in low-power modes.

The data cache of the STM32U5, which speeds up data accesses of the Cortex-M33 to external memories.

Two-dimensional addressing on the DMA channels of the STM32U5 that support it: moving blocks of data with strides, for example a rectangle of an image.

DMA transfers that continue while the STM32U5 is in a low-power mode, driven by peripheral requests without waking the CPU.

Circular buffering and double buffering with the DMA of the STM32U5, built from linked-list items.

How the DMA of the STM32U5 reports errors: the error types, their flags and the state of the channel after an error.

Control of the input and output of the linked-list items in the DMA of the STM32U5: how the channel loads the next item and signals its end.

Linked-list programming of the DMA of the STM32U5: a chain of transfer descriptors in memory that the channel runs without the CPU.

An overview of the general-purpose DMA of the STM32U5: its channels, ports and the features detailed in the other DMA modules.

The registers of a DMA channel of the STM32U5 and how each transfer setting maps to them.

DMA transfers of the STM32U5 seen from the hardware and from the software: bursts, data widths, packing and the HAL calls that set them up.

The extended interrupt and event controller of the STM32U5, with lines that can be set secure or privileged.

The GPIO ports of the STM32U5 and the low-power GPIO that stays usable in Stop 2 mode for autonomous peripherals.

The instruction cache of the STM32U5, between the Cortex-M33 and the internal and external memories.

The power controller of the STM32U5: supplies, voltage regulation and low-power modes. Depending on the part, the core is supplied by an LDO or an SMPS step-down converter; several Stop modes keep the SRAM content.

The reset and clock controller of the STM32U5: the clock sources, the PLL and the clock tree of the system and peripherals. The clocks of the peripherals that work in Stop modes are covered too.

The consumption of the STM32U5 measured with the ULPMark-PeripheralProfile benchmark, and the low-power background autonomous mode (LPBAM) in which peripherals and DMA work while the CPU is stopped.

The embedded Flash memory of the STM32U5: organisation, read access, programming and erase. The Flash has two banks and supports TrustZone and ECC.

The RAM configuration controller of the STM32U5: ECC on the SRAMs, write protection, erase and wait states.

Asymmetric cryptography on the STM32U5 with the public key accelerator: RSA and elliptic curve operations.

An introduction to the cryptographic peripherals of the STM32U5 and the role of each one. Depending on the part, the STM32U5 has AES, SAES, HASH, PKA and RNG units.

The STM32 cryptographic library on the STM32U5: the algorithms it provides and how it uses the hardware accelerators.

How the STM32U5 protects keys: hardware unique keys, keys that software never reads and the secure AES unit.

The hash processor and the random number generator of the STM32U5.

An overview of the security features of the STM32U5 and how they fit together in a secure product.

The root security services of the STM32U5: code in system memory that the device runs at reset, such as the secure installation of firmware.

The security certifications obtained for the STM32U5 and what they mean for a product built on it.

Symmetric cryptography on the STM32U5: the AES and SAES units and their chaining modes.

The Flash memory used by Trusted Firmware-M on the STM32U5, and how the layout of the Flash is set.

An introduction to Trusted Firmware-M (TFM), the reference secure software for Armv8-M, as provided for the STM32U5.

What the STM32Cube package of the STM32U5 provides around Trusted Firmware-M.

The time the secure boot of Trusted Firmware-M takes on the STM32U5, and what it depends on.

Where to find the documentation, sources and examples of Trusted Firmware-M for the STM32U5.

The analog-to-digital and digital-to-analog converters of the STM32U5, including the ADC that works in low-power modes.

An overview of the analog peripherals of the STM32U5 and of the modules that describe them.

The analog comparators of the STM32U5: input selection, output routing and use as a wake-up source.

The operational amplifiers of the STM32U5: standalone use, follower and programmable gain modes.

The voltage reference buffer of the STM32U5, which supplies the reference voltage of the ADC and DAC and can output it on a pin.

The low-power timer of the STM32U5, which keeps counting in Stop modes with a low-frequency clock or external pulses.

The multi-function digital filter and the audio digital filter of the STM32U5, which process the bit streams of sigma-delta modulators and digital microphones.

The STM32Cube firmware package of the STM32U5: drivers, middleware and examples.

The tools and software that support the STM32U5: STM32Cube configuration and programming tools, the firmware package and the boards.

The Arm Cortex-M33 processor as integrated in the STM32L5: an Armv8-M core with TrustZone, a floating-point unit and DSP instructions, running up to 110 MHz.

How the STM32L5 selects its boot address, with or without TrustZone enabled.

The debug support of the STM32L5: the Serial Wire Debug port, breakpoints and watchpoints, and how debug behaves in low-power modes. With TrustZone, debug access to the secure world is controlled separately.

The DMA controller of the STM32L5: memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers that leave the CPU free.

The extended interrupt and event controller of the STM32L5: GPIO and peripheral lines that raise interrupts or events, including wake-up from low-power modes. Each line can be set secure or non-secure.

The instruction cache of the STM32L5, which speeds up code run from the internal Flash and from external memory.

The interconnect matrix of the STM32L5: the direct connections between peripherals that work without the CPU or the DMA.

The nested vectored interrupt controller of the Cortex-M33 in the STM32L5: interrupt priorities, preemption and the vector table.

The power controller of the STM32L5: supplies, voltage regulation and low-power modes. Some parts add an SMPS step-down converter to lower the consumption.

The reset and clock controller of the STM32L5: the clock sources, the PLL and the clock tree of the system and peripherals. The clock settings can be restricted to the secure world.

The system configuration controller of the STM32L5: memory remapping and the settings of the system that do not belong to one peripheral.

The tamper detection and backup registers of the STM32L5: inputs that detect an intrusion and the registers kept when the main supply is off.

The embedded Flash memory of the STM32L5: organisation, read access, programming and erase. With TrustZone, parts of the Flash are declared secure by watermarks in the option bytes.

The flexible static memory controller of the STM32L5, for external SRAM, PSRAM, NOR and NAND memories and LCD modules.

The OCTOSPI interface of the STM32L5, which connects serial Flash and RAM memories on one, two, four or eight data lines.

The on-the-fly decryption engine of the STM32L5, which decrypts code and data read from external memory through the OCTOSPI.

TrustZone on the STM32L5: how memories, peripherals and interrupts are divided between the secure and the non-secure world.

The DFSDM of the STM32L5, which filters the bit streams of external sigma-delta modulators and digital microphones.

The FDCAN controller of the STM32L5: CAN 2.0 and CAN FD frames with a flexible data rate.

The global TrustZone controller of the STM32L5, which sets the security of the peripherals and of the internal and external memories.

The serial audio interface of the STM32L5, for audio codecs and digital microphones.

The touch sensing controller of the STM32L5, which measures capacitive sensors for buttons, sliders and wheels.

The USB Type-C and Power Delivery controller of the STM32L5: cable detection on the CC lines and the Power Delivery messages.

The timers of the STM32L5: counting modes, input capture, output compare and PWM. The series has advanced-control, general-purpose and basic timers.

The real-time clock of the STM32L5: calendar, alarms and wake-up timer, kept running in low-power modes and on VBAT.

The Arm Cortex-M4 processor as integrated in the STM32G4: a core with DSP instructions and a single-precision floating-point unit, running up to 170 MHz.

The debug support of the STM32G4: the Serial Wire Debug port, breakpoints and watchpoints, and how debug behaves in low-power modes. The Cortex-M4 adds instrumentation trace output on the SWO pin.

The extended interrupt and event controller of the STM32G4: GPIO and peripheral lines that raise interrupts or events, including wake-up from low-power modes.

The general-purpose I/O ports of the STM32G4: pin modes, output drive and alternate functions.

The interconnect matrix of the STM32G4: the direct connections between peripherals that work without the CPU or the DMA.

The nested vectored interrupt controller of the Cortex-M4 in the STM32G4: interrupt priorities, preemption and the vector table.

The power controller of the STM32G4: supplies, voltage regulation and low-power modes. The regulator has a boost mode for the highest frequency.

The reset and clock controller of the STM32G4: the clock sources, the PLL and the clock tree of the system and peripherals. The 48 MHz internal oscillator for USB is trimmed by the clock recovery system.

The system configuration controller of the STM32G4: memory remapping and the settings of the system that do not belong to one peripheral.

The tamper detection and backup registers of the STM32G4: inputs that detect an intrusion and the registers kept when the main supply is off.

The embedded Flash memory of the STM32G4: organisation, read access, programming and erase. Depending on the part, the Flash has one or two banks.

The flexible memory controller of the STM32G4, which connects external SRAM, PSRAM, NOR and NAND memories and LCD modules.

The protections of the memories of the STM32G4: how code and data are protected against reading, writing or debug access.

The analog-to-digital converters of the STM32G4: 12-bit successive-approximation ADCs with up to 4 Msps per ADC and hardware oversampling.

The analog comparators of the STM32G4: input selection, output routing and use as a wake-up source.

The digital-to-analog converter of the STM32G4: output modes, triggers and waveform generation. The STM32G4 has buffered DAC channels for external loads and fast unbuffered channels for internal use.

The voltage reference buffer of the STM32G4, which supplies the reference voltage of the ADC and DAC and can output it on a pin.

The CORDIC co-processor of the STM32G4, which computes trigonometric, hyperbolic and other mathematical functions in fixed point.

The filter math accelerator of the STM32G4, which runs FIR and IIR filters and vector operations in hardware.

The FDCAN controller of the STM32G4: CAN 2.0 and CAN FD frames with a flexible data rate.

The low-power UART of the STM32G4, which keeps receiving serial data in Stop mode with a 32.768 kHz clock.

The USART of the STM32G4: asynchronous and synchronous serial communication and the protocols built on it.

The USB Type-C and Power Delivery controller of the STM32G4: cable detection on the CC lines and the Power Delivery messages.

The infrared interface of the STM32G4, which combines two timer outputs to drive an infrared LED for remote controls.

The timers of the STM32G4: counting modes, input capture, output compare and PWM. The STM32G4 timers include motor-control features and encoder interfaces.

The STM32Cube firmware package of the STM32G4: drivers, middleware and examples.

The ST boards available for the STM32G4, from the Nucleo boards to the evaluation boards.

The opening module of the STM32G0 online training: how the training is organised and where to start.

The Arm Cortex-M0+ processor as integrated in the STM32G0: a 32-bit core with a two-stage pipeline, running up to 64 MHz.

The debug support of the STM32G0: the Serial Wire Debug port, breakpoints and watchpoints, and how debug behaves in low-power modes.

The DMA controller of the STM32G0: memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers that leave the CPU free.

The DMA request multiplexer of the STM32G0, which connects any peripheral request to any DMA channel.

The extended interrupt and event controller of the STM32G0: GPIO and peripheral lines that raise interrupts or events, including wake-up from low-power modes.

The general-purpose I/O ports of the STM32G0: pin modes, output drive and alternate functions.

The interconnect matrix of the STM32G0: the direct connections between peripherals that work without the CPU or the DMA.

The nested vectored interrupt controller of the Cortex-M0+ in the STM32G0: interrupt priorities, preemption and the vector table.

The power controller of the STM32G0: supplies, voltage regulation and low-power modes. The module also covers the brown-out and programmable voltage detectors.

The tamper detection and backup registers of the STM32G0: inputs that detect an intrusion and the registers kept when the main supply is off.

The embedded Flash memory of the STM32G0: organisation, read access, programming and erase. The Flash is read with 64-bit words and an ECC on each word.

The AES hardware accelerator of the STM32G0: encryption and decryption with 128-bit or 256-bit keys.

The protections of the memories of the STM32G0: how code and data are protected against reading, writing or debug access.

The analog comparators of the STM32G0: input selection, output routing and use as a wake-up source.

The digital-to-analog converter of the STM32G0: output modes, triggers and waveform generation.

The voltage reference buffer of the STM32G0, which supplies the reference voltage of the ADC and DAC and can output it on a pin.

The serial peripheral interface of the STM32G0: master and slave modes, data frames and the I2S audio mode.

The USART of the STM32G0: asynchronous and synchronous serial communication and the protocols built on it.

The USB Type-C and Power Delivery controller of the STM32G0: cable detection on the CC lines and the Power Delivery messages.

The timers of the STM32G0: counting modes, input capture, output compare and PWM. The series has advanced-control, general-purpose and basic timers.

The infrared interface of the STM32G0, which combines two timer outputs to drive an infrared LED for remote controls.

The real-time clock of the STM32G0: calendar, alarms and wake-up timer, kept running in low-power modes and on VBAT.

STM32CubeMX applied to the STM32G0: choosing the part, setting pins, clocks and peripherals, and generating the initialisation code.

The ST boards available for the STM32G0, from the Nucleo boards to the evaluation boards.