For dedicated sessions at your training facilities, content can be tailored to further meet your needs
(Contact us for public workshops)
Certificate of Completion
A Certificate of Completion will be delivered upon completion of the training course
This course aims to enable participants to design, verify or debug CXL IPs and links. Participants get a detailed understanding of the following protocol: CXL 3.0. The attendees will learn about CXL hardware and software implementation which is explained through multiple use cases. Management of accelerators and memory expanders is covered.
Prerequisites and related courses
Knowledge of PCIe gen6 is mandatory, see our course CVT_GP_PCIE6
- Bias management
- .mem, Back Invalidation new CXL 3.0 feature
ARB / MUX
RESET, INITIALIZATION, CONFIGURATION AND MANAGEABILITY
RELIABILITY, AVAILABILITY AND SERVICEABILITY
MOVE.B IS MORE THAN A TRAINING CENTER
Trainers are also experts able to assist customers throughout the design process.
They also provide consulting services, design support and assistance.
Therefore, our trainers contribute to the success of our customers’ industrial projects by leveraging all of the technologies they master and teach.