CXL
Reference : CVT_GP_CXL
Course families : Connectivity > General purpose buses
Target Audience : Architects, board designers, verification engineers, firmware developers
Duration : 3 days, 7 hours a day
Reference : CVT_GP_CXL
Course families : Connectivity > General purpose buses
Target Audience : Architects, board designers, verification engineers, firmware developers
Duration : 3 days, 7 hours a day
INTRODUCTION
SYSTEM ARCHITECTURE
- Bias management
PHYSICAL LAYER
LINK LAYER
TRANSACTION LAYER
- .i:o
- .cache
- .mem, Back Invalidation new CXL 3.0 feature
ARB / MUX
SWITCHES
RESET, INITIALIZATION, CONFIGURATION AND MANAGEABILITY
POWER MANAGEMENT
SECURITY
RELIABILITY, AVAILABILITY AND SERVICEABILITY
PERFORMANCE CONSIDERATIONS
COMPLIANCE TESTING
Lectures with supporting slides, demos and case studies.
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content