Reference : NXP_MC
Course families : Processors > NXP CPUs, MCUs and MPUs > NXP Arm- and POWER-based multicore architecture
Target Audience : Software architects Software developers Certification engineers
Duration : 3 days, 7 hours a day
INTRODUCTION TO MULTICORE CONCEPTS
NXP MULTICORE PLATFORMS
VIRTUALIZATION
CACHE COHERENCY
SHARED RESOURCE MANAGEMENT
EXCEPTION MANAGEMENT
SPATIAL ISOLATION, PROCESSOR MMU
SPATIAL ISOLATION, IO MMU
INTERCONNECT
DEBUGGING A MULTICORE SYSTEM
Lectures with supporting slides, demos and case studies
Review and execution of practical examples, provided by MOVE.B, using GCC compiler and Lauterbach Trace32 debugger
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
