Reference : NXP_ARM_IMXRT1064
Course families : NXP Arm MPUs > i.MX MPUs and MCUs > i.MXRT
Target Audience : Board designers, boot and driver software developers
Duration : 5 days, 7 hours a day
ARCHITECTURE OF i.MXRT1020, 1040, 1050, 1060 AND 1064
INTERCONNECT
ON-CHIP CROSS TRIGGERS
POWER, CLOCKING AND RESET
MEMORY CONTROLLERS
TIMERS
ENHANDED DMA (eDMA)
ANALOG MODULES
ULTRA SECURED DIGITAL HOST CONTROLLER (uSDHC)
USB CONTROLLERS
VIDEO INTERFACES
COMMUNICATION MODULES
VIDEO AND GRAPHICS MODULES
AUDIO MODULES
SECURITY OVERVIEW
CENTRAL SECURITY UNIT (CSU)
SECURE NON VOLATILE STORAGE (SNVS)
TRUE RANDOM NUMBER GENERATOR
DATA CO-PROCESSOR (DCP)
BUS ENCRYPTION ENGINE (BEE)
HIGH ASSURANCE BOOT
Lectures with supporting slides, demos and case studies
Review and execution of practical examples, provided by MOVE.B, using GCC compiler and Lauterbach Trace32 debugger
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
