Reference : CVT_GP_UCIE
Course families : Connectivity > General purpose busesConnectivity
Target Audience : Architects, SoC designers, verification engineers, firmware developers
Duration : 1 day, 7 hours a day
INTRODUCTION
ELECTRICAL LAYER
LOGICAL PHYSICAL LAYER
DIE-TO-DIE ADAPTER
PROTOCOL LAYER
SIDEBAND
CONFIGURATION
Lectures with supporting slides, demos and case studies.
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
CXL HYPERBUS