Reference : POWER_CPU_E500
Course families : NXP CPUs, MCUs and MPUs > NXP POWER CPUs and MPUs > POWER CPUs
Target Audience : Software developers
Duration : 4 days, 7 hours a day
OVERVIEW
INSTRUCTION PIPELINE
CLOCKING AND POWER MANAGEMENT
EXCEPTION MECHANISM
DATA AND INSTRUCTION PATHS
MEMORY MANAGEMENT UNIT
L1 CACHES
HARDWARE CACHE COHERENCY
DEBUG
ASSEMBLY INSTRUCTIONS
EABI
FLOATING-POINT UNIT
SIGNAL PROCESSING ENGINE (SPE)
Lectures with supporting slides, demos and case studies
Review and execution of practical examples, provided by MOVE.B, using GCC compiler and Lauterbach Trace32 debugger
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
E300 E500MC