Reference : R5_64B_U54
Course families : Processors > RISC-V processor
Target Audience : Architects, verification engineers, software developers
Duration : 3 days, 7 hours a day
U54 & U74 CPU ARCHITECTURE
INSTRUCTION PIPELINE
PRIVILEGE MODES AND MEMORY PROTECTION
SIFIVE WORLDGUARD
EXCEPTION MECHANISM
CORE LOCAL INTERRUPTOR (CLINT)
PLATFORM-LEVEL INTERRUPT CONTROLLER- (PLIC)
MEMORY MANAGEMENT UNIT
DATA AND INSTRUCTION PATHS
TIGHTLY INTEGRATED MEMORY
CACHES
POWER MANAGEMENT
SUPERVISOR PROGRAMMING
USER PROGRAMMING
FLOATING-POINT UNIT
COMPILER OPTIONS
OPENSBI
DEBUG FEATURES
Lectures with supporting slides, use of projector.
Review and execution of practical examples, provided by MOVE.B, using the GCC toolchain.
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
32-BIT RISC-V E31