For dedicated sessions at your training facilities, content can be tailored to further meet your needs
(Contact us for public workshops)
Certificate of Completion
A Certificate of Completion will be delivered upon completion of the training course
This course explains the hardware and software architecture of the Risc-V U54 and U74 cores to enable participants to efficiently design a SoC based on this CPU, verify it, and develop low level software, implementing the features offered by the CPU: exceptions, low power modes, assembly language.
Prerequisites and related courses
Basic knowledge of a CPU or DSP.
For integration into a Soc, see ARM_AMBA_AXI.
Based on ICICLE board, GCC toolchain and Trace32 debugger
U54 & U74 CPU ARCHITECTURE
PRIVILEGE MODES AND MEMORY PROTECTION
CORE LOCAL INTERRUPTOR (CLINT)
PLATFORM-LEVEL INTERRUPT CONTROLLER- (PLIC)
MEMORY MANAGEMENT UNIT
DATA AND INSTRUCTION PATHS
TIGHTLY INTEGRATED MEMORY
MOVE.B IS MORE THAN A TRAINING CENTER
Trainers are also experts able to assist customers throughout the design process.
They also provide consulting services, design support and assistance.
Therefore, our trainers contribute to the success of our customers’ industrial projects by leveraging all of the technologies they master and teach.