32-BIT RISC-V E31
Reference : R5_32B_E31
Course families : Processors > RISC-V processor
Target Audience : Architects, verification engineers, software developers
Duration : 2 days, 7 hours a day
Reference : R5_32B_E31
Course families : Processors > RISC-V processor
Target Audience : Architects, verification engineers, software developers
Duration : 2 days, 7 hours a day
CPU ARCHITECTURE
HARDWARE IMPLEMENTATION
INSTANTIATING THE CORE
DATA AND INSTRUCTION PATHS
CACHES
EXCEPTION MECHANISM
PLATFORM-LEVEL INTERRUPT CONTROLLER- PLIC
SUPERVISOR PROGRAMMING
USER PROGRAMMING
DEBUG FEATURES
Lectures with supporting slides, demos and case studies.
Review and execution of practical examples, provided by MOVE.B, using the GCC toolchain.
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content