Reference : R5_64B_SF_UCORES
Course families : Processors > RISC-V Processors > RISC-V SIFIVE CORES
Target Audience : Architects, verification engineers, software developers
Duration : 3 days, 7 hours a day
U54 AND U74 CPU ARCHITECTURE
INSTRUCTION PIPELINE
PRIVILEGE MODES AND MEMORY PROTECTION
USER PROGRAMMING
FLOATING-POINT UNIT
SUPERVISOR PROGRAMMING
COMPILER OPTIONS
EXCEPTION MECHANISM
CORE LOCAL INTERRUPTOR (CLINT)
PLATFORM-LEVEL INTERRUPT CONTROLLER- (PLIC)
POWER MANAGEMENT
DATA AND INSTRUCTION PATHS
MEMORY MANAGEMENT UNIT
CACHES
U54 TIGHTLY INTEGRATED MEMORY
OPENSBI
DEBUG FEATURES
Lectures with supporting slides.
Review and execution of practical examples, provided by MOVE.B, using the GCC toolchain, and Trace32 Lauterbach debugger.
Trainees will participate in quizzes and learning checks throughout the course.
Each trainee will fill out and return a training evaluation form upon completion of the training course
Our trainers regularly attend train-the-trainer courses with our partners to continuously improve their technical skills and knowledge on the latest components, technologies, and upcoming releases
Each attendee will receive a Participant Guide (in a pdf format)
Learners should bring their laptops to the course; they will be able to navigate in the presentation and access the training content
RISC-V 64-BIT E51 RISC-V SIFIVE 64-BIT S-CORES